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MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
15 years 4 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
SC
1995
ACM
15 years 3 months ago
A Performance Evaluation of the Convex SPP-1000 Scalable Shared Memory Parallel Computer
The Convex SPP-1000 is the first commercial implementation of a new generation of scalable shared memory parallel computers with full cache coherence. It employs a hierarchical s...
Thomas L. Sterling, Daniel Savarese, Peter MacNeic...
WCET
2010
14 years 9 months ago
Bounding the Effects of Resource Access Protocols on Cache Behavior
The assumption of task independence has long been consubstantial with the formulation of many schedulability analysis techniques. That assumption is evidently advantageous for the...
Enrico Mezzetti, Marco Panunzio, Tullio Vardanega
NCA
2003
IEEE
15 years 5 months ago
Web Proxy Cache Replacement: Do's, Don'ts, and Expectations
Numerous research efforts have produced a large number of algorithms and mechanisms for web proxy caches. In order to build powerful web proxies and understand their performance, ...
Peter Triantafillou, Ioannis Aekaterinidis
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 5 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood