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ISCA
2000
IEEE
107views Hardware» more  ISCA 2000»
15 years 1 months ago
A fully associative software-managed cache design
As DRAM access latencies approach a thousand instructionexecution times and on-chip caches grow to multiple megabytes, it is not clear that conventional cache structures continue ...
Erik G. Hallnor, Steven K. Reinhardt
79
Voted
ANCS
2009
ACM
14 years 7 months ago
EINIC: an architecture for high bandwidth network I/O on multi-core processors
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
Guangdeng Liao, Laxmi N. Bhuyan, Danhua Guo, Steve...
IPPS
2005
IEEE
15 years 3 months ago
Effective Instruction Prefetching via Fetch Prestaging
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
Ayose Falcón, Alex Ramírez, Mateo Va...
86
Voted
TCAD
2008
88views more  TCAD 2008»
14 years 9 months ago
Self-Adaptive Data Caches for Soft-Error Reliability
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
Shuai Wang, Jie S. Hu, Sotirios G. Ziavras
75
Voted
FAST
2010
14 years 12 months ago
I/O Deduplication: Utilizing Content Similarity to Improve I/O Performance
Duplication of data in storage systems is becoming increasingly common. We introduce I/O Deduplication, a storage optimization that utilizes content similarity for improving I/O p...
Ricardo Koller, Raju Rangaswami