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ICCAD
2003
IEEE
113views Hardware» more  ICCAD 2003»
15 years 7 months ago
Retiming with Interconnect and Gate Delay
In this paper, we study the problem of retiming of sequential circuits with both interconnect and gate delay. Most retiming algorithms have assumed ideal conditions for the non-lo...
Chris C. N. Chu, Evangeline F. Y. Young, Dennis K....
DATE
2009
IEEE
86views Hardware» more  DATE 2009»
15 years 4 months ago
A formal approach to design space exploration of protocol converters
In the field of chip design, hardware module reuse is a standard solution to the increasing complexity of chip architecture and the pressures to reduce time to market. In the abs...
Karin Avnit, Arcot Sowmya
NTMS
2009
IEEE
15 years 4 months ago
Minimizing Cost of Scalable Distributed Least Squares Localization
—Wireless Sensor Networks (WSNs) have been of high interest during the past couple of years. One of the most important aspects of WSN research is location estimation. As a good s...
Ralf Behnke, Jakob Salzmann, Dirk Timmermann
ICST
2009
IEEE
15 years 4 months ago
Optimizing Generation of Object Graphs in Java PathFinder
Java PathFinder (JPF) is a popular model checker for Java programs. JPF was used to generate object graphs as test inputs for object-oriented programs. Specifically, JPF was used...
Milos Gligoric, Tihomir Gvero, Steven Lauterburg, ...
GECCO
2009
Springer
101views Optimization» more  GECCO 2009»
15 years 4 months ago
Modeling UCS as a mixture of experts
We present a probabilistic formulation of UCS (a sUpervised Classifier System). UCS is shown to be a special case of mixture of experts where the experts are learned independentl...
Narayanan Unny Edakunni, Tim Kovacs, Gavin Brown, ...