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» Simple But Effective Techniques for NUMA Memory Management
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73
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MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
15 years 6 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
EUROPAR
1999
Springer
15 years 4 months ago
Annotated Memory References: A Mechanism for Informed Cache Management
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
Alvin R. Lebeck, David R. Raymond, Chia-Lin Yang, ...
MICRO
2006
IEEE
162views Hardware» more  MICRO 2006»
15 years 5 months ago
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
Ranjith Subramanian, Yannis Smaragdakis, Gabriel H...
VLDB
2001
ACM
119views Database» more  VLDB 2001»
15 years 12 months ago
PicoDBMS: Scaling down database techniques for the smartcard
Smartcards are the most secure portable computing device today. They have been used successfully in applications involving money, proprietary and personal data (such as banking, h...
Philippe Pucheral, Luc Bouganim, Patrick Valduriez...
85
Voted
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
15 years 6 months ago
Architectural leakage-aware management of partitioned scratchpad memories
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be ev...
Olga Golubeva, Mirko Loghi, Massimo Poncino, Enric...