41 search results - page 2 / 9 » Simulated Annealing Based Temperature Aware Floorplanning |
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
TCAD
2010
14 years 4 months ago
2010
In this paper, we present DeFer--a fast, high-quality, scalable, and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a nonslicing floorplan by compacting a sli...
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IPPS
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper analyses alternatives for the parallelization of the Simulated Annealing algorithm when applied to the placement of modules in a VLSI circuit considering the use of PVM...
RSP
1999
IEEE
15 years 1 months ago
1999
IEEE
The advances in the programmable hardware has lead to new architectures where the hardware can be dynamically adapted to the application to gain better performance. There are stil...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
— In this paper, we present the first multi-objective microarchitectural floorplanning algorithm for designing highperformance, high-reliability processors in the early design ...