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DAC
2001
ACM
15 years 10 months ago
A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs
Due to larger buses (length, width) and deep sub-micron effects where coupling capacitances between bus lines are in the same order of magnitude as base capacitances, power consum...
Haris Lekatsas, Jörg Henkel
ICCD
2000
IEEE
69views Hardware» more  ICCD 2000»
15 years 2 months ago
Hierarchical Simulation of a Multiprocessor Architecture
When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware ...
Marius Pirvu, Laxmi N. Bhuyan, Rabi N. Mahapatra
ICANN
1997
Springer
15 years 1 months ago
Minimalistic Approach to 3D Obstacle Avoidance Behavior from Simulated Evolution
We present a minimalistic approach to establish obstacle avoidance and course stabilization behavior of a simulated flying autonomous agent in a 3D virtual world. The agent uses v...
Titus R. Neumann, Susanne A. Huber, Heinrich H. B&...
DATE
2009
IEEE
101views Hardware» more  DATE 2009»
15 years 4 months ago
A monitor interconnect and support subsystem for multicore processors
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burl...
IPPS
2000
IEEE
15 years 2 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis