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APCSAC
2003
IEEE
15 years 9 months ago
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main mem...
Philip Machanick, Zunaid Patel
CCR
1998
107views more  CCR 1998»
15 years 3 months ago
Reinforcement of TCP error recovery for wireless communication
When a wireless link forms a part of a network, the rate of packet loss due to link noise may be considerably higher than observed in a modern terrestrial network. This paper stud...
Nihal K. G. Samaraweera, Godred Fairhurst
ETFA
2005
IEEE
15 years 9 months ago
LEF closed-loop scheduling policy for real-time control systems
Today there is a significant body of results of resource management in real-time systems. However, most of them are based on "open-loop" strategies and techniques that do...
J. Yepez, Pau Martí, J. Ayza, Josep M. Fuer...
DIGRA
2005
Springer
15 years 9 months ago
Making Right(s) Decision: Artificial life and Rights Reconsidered
With the proliferation of robotics in industry, education and entertainment, artificial intelligent robots challenge the way we think about relationships between humans and machin...
Juyun Kim
SAMOS
2005
Springer
15 years 9 months ago
Micro-architecture Performance Estimation by Formula
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
Lucanus J. Simonson, Lei He