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ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
16 years 1 months ago
Guaranteeing performance yield in high-level synthesis
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current hi...
Wei-Lun Hung, Xiaoxia Wu, Yuan Xie
ICCAD
2005
IEEE
120views Hardware» more  ICCAD 2005»
16 years 1 months ago
Practical techniques to reduce skew and its variations in buffered clock networks
Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variation...
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, P...
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
16 years 1 months ago
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
15 years 11 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...
DASFAA
2009
IEEE
203views Database» more  DASFAA 2009»
15 years 11 months ago
Adaptive Safe Regions for Continuous Spatial Queries over Moving Objects
Abstract. Continuous spatial queries retrieve a set of time-varying objects continuously during a given period of time. However, monitoring moving objects to maintain the correctne...
Yu-Ling Hsueh, Roger Zimmermann, Wei-Shinn Ku