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IEEEPACT
1999
IEEE
15 years 2 months ago
The Effect of Program Optimization on Trace Cache Efficiency
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
Derek L. Howard, Mikko H. Lipasti
ASPLOS
2008
ACM
14 years 11 months ago
Streamware: programming general-purpose multicore processors using streams
Recently, the number of cores on general-purpose processors has been increasing rapidly. Using conventional programming models, it is challenging to effectively exploit these core...
Jayanth Gummaraju, Joel Coburn, Yoshio Turner, Men...
SIGADA
2007
Springer
15 years 3 months ago
AADL modeling and analysis of hierarchical schedulers
A system based on a hierarchical scheduler is a system in which the processor is shared between several collaborative schedulers. Such schedulers exist since 1960 and they are bec...
Frank Singhoff, Alain Plantec
MICRO
2002
IEEE
100views Hardware» more  MICRO 2002»
15 years 2 months ago
Microarchitectural exploration with Liberty
To find the best designs, architects must rapidly simulate many design alternatives and have confidence in the results. Unfortunately, the most prevalent simulator construction ...
Manish Vachharajani, Neil Vachharajani, David A. P...
IJHPCA
2008
131views more  IJHPCA 2008»
14 years 9 months ago
De Novo Ultrascale Atomistic Simulations On High-End Parallel Supercomputers
We present a de novo hierarchical simulation framework for first-principles based predictive simulations of materials and their validation on high-end parallel supercomputers and ...
Aiichiro Nakano, Rajiv K. Kalia, Ken-ichi Nomura, ...