1366 search results - page 44 / 274 » Simulation Modeling and Optimization using ProModel |
88
Voted
FPGA
2008
ACM
14 years 11 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
107
Voted
PATMOS
2007
Springer
15 years 4 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
106
Voted
ISQED
2011
IEEE
14 years 1 months ago
2011
IEEE
—Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-s...
WSC
2007
15 years 15 days ago
2007
This paper describes an innovative framework, iFAOSimo, which integrates optimization, simulation and GIS (geographic information system) techniques to handle complex spatial faci...
108
Voted
PE
2002
Springer
14 years 9 months ago
2002
Springer
In this paper, we study the use of continuous-time hidden Markov models (CT-HMMs) for network protocol and application performance evaluation. We develop an algorithm to infer the...