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ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
14 years 5 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
HIPEAC
2011
Springer
14 years 1 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
IISWC
2008
IEEE
15 years 8 months ago
Characterizing and improving the performance of Intel Threading Building Blocks
Abstract— The Intel Threading Building Blocks (TBB) runtime library [1] is a popular C++ parallelization environment [2][3] that offers a set of methods and templates for creatin...
Gilberto Contreras, Margaret Martonosi
ICIP
1998
IEEE
16 years 3 months ago
B-spline Snakes and a JAVA Interface: An Intuitive Tool for General Contour Outlining
We present a novel formulation for B-spline snakes that can be used as a tool for fast and intuitive contour outlining. The theory is implemented in a platform independent JAVA in...
Patrick Brigger, Robert Engel, Michael Unser
73
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ICPR
2004
IEEE
16 years 2 months ago
Efficient Coding of Stroke-Rendered Paintings
There are more and more applications of nonphotorealistic rendered images, sketches and drawings. Several techniques for generating such imagery are widely known. The stochastic p...
Levente Kovács, Tamás Szirány...