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CODES
2007
IEEE
16 years 24 days ago
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the targ...
Brett H. Meyer, Donald E. Thomas
173
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ESTIMEDIA
2007
Springer
16 years 18 days ago
Leveraging Predicated Execution for Multimedia Processing
—Modern compression standards such as H.264, DivX, or VC-1 provide astonishing quality at the costs of steadily increasing processing requirements. Therefore, efficient solution...
Dietmar Ebner, Florian Brandner, Andreas Krall
CGO
2006
IEEE
16 years 15 days ago
Compiling for EDGE Architectures
Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
Aaron Smith, Jon Gibson, Bertrand A. Maher, Nichol...
GLOBECOM
2006
IEEE
16 years 15 days ago
Packet Delay-Aware Scheduling in Input Queued Switches
Abstract— Virtual Output Queuing is widely used by highspeed packet switches to overcome head-of-line blocking. This is done by means of matching algorithms. In fixed-length VOQ...
Yihan Li, Shivendra S. Panwar, H. Jonathan Chao, J...
IWCMC
2006
ACM
16 years 12 days ago
A heuristics based approach for cellular mobile network planning
Designing and planning of the switching, signaling and support network is a fairly complex process in cellular mobile network. In this paper, the problem of assigning cells to swi...
Marwan H. Abu-Amara, Sadiq M. Sait, Abdul Subhan