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ISCAS
1994
IEEE
138views Hardware» more  ISCAS 1994»
15 years 9 months ago
High-Throughput Data Compressor Designs Using Content Addressable Memory
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
Ren-Yang Yang, Chen-Yi Lee
157
Voted
ASPLOS
1992
ACM
15 years 9 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
PODC
1994
ACM
15 years 9 months ago
A Performance Evaluation of Lock-Free Synchronization Protocols
In this paper, we investigate the practical performance of lock-free techniques that provide synchronization on shared-memory multiprocessors. Our goal is to provide a technique t...
Anthony LaMarca
151
Voted
SIGMETRICS
1993
ACM
118views Hardware» more  SIGMETRICS 1993»
15 years 9 months ago
An Analytic Performance Model of Disk Arrays
As disk arrays become widely used, tools for understanding and analyzing their performance become increasingly important. In particular, performance models can be invaluable in bo...
Edward K. Lee, Randy H. Katz
187
Voted
SIGMETRICS
1992
ACM
145views Hardware» more  SIGMETRICS 1992»
15 years 9 months ago
Analysis of the Generalized Clock Buffer Replacement Scheme for Database Transaction Processing
The CLOCK algorithm is a popular buffer replacement algorithm becauseof its simplicity and its ability to approximate the performance of the Least Recently Used (LRU) replacement ...
Victor F. Nicola, Asit Dan, Daniel M. Dias
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