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» Simulation of Soliton Circuits
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UMC
2000
15 years 1 months ago
In-vitro Transcriptional Circuits
The structural similarity of neural networks and genetic regulatory networks to digital circuits, and hence to each other, was noted from the very beginning of their study [1, 2]....
Erik Winfree
GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
14 years 12 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
DAC
1999
ACM
15 years 11 months ago
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
ICCAD
2004
IEEE
80views Hardware» more  ICCAD 2004»
15 years 7 months ago
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization
We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the res...
Jintae Kim, Jaeseo Lee, Lieven Vandenberghe
ICCAD
2001
IEEE
84views Hardware» more  ICCAD 2001»
15 years 7 months ago
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits
Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don’...
Seiji Kajihara, Kohei Miyase