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» Simulation of Soliton Circuits
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74
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ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
15 years 4 months ago
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
Bao Liu
WSC
2000
14 years 11 months ago
Modeling reality with simulation games for a cooperative learning
In this work we want to show the importance of visualization, interfaces and re-design techniques through 3D modeling, animations and VRML in the developing of the simulation game...
João Rafael Galvão, Paulo Garcia Mar...
ASPDAC
2000
ACM
111views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Gate-level aged timing simulation methodology for hot-carrier reliability assurance
- This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a un...
Yoshiyuki Kawakami, Jingkun Fang, Hirokazu Yonezaw...
89
Voted
FPGA
2003
ACM
116views FPGA» more  FPGA 2003»
15 years 3 months ago
Hardware-assisted simulated annealing with application for fast FPGA placement
To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand p...
Michael G. Wrighton, André DeHon
97
Voted
TACAS
1998
Springer
98views Algorithms» more  TACAS 1998»
15 years 2 months ago
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation
This paper enables symbolic ternary simulation of systems with large embedded memories. Each memory array is replaced with a behavioral model, where the number of symbolic variable...
Miroslav N. Velev, Randal E. Bryant