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» Simulation of Soliton Circuits
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DATE
2009
IEEE
98views Hardware» more  DATE 2009»
15 years 5 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
76
Voted
ISMVL
2007
IEEE
90views Hardware» more  ISMVL 2007»
15 years 4 months ago
Quantum Robots for Teenagers
Extending the ideas of Quantum Braitenberg Vehicles from [14], we present here a family of Lego robots controlled by multiple-valued quantum circuits. The robots have at most 6 de...
Arushi Raghuvanshi, Yale Fan, Michal Woyke, Marek ...
93
Voted
CTRSA
2005
Springer
88views Cryptology» more  CTRSA 2005»
15 years 3 months ago
Side-Channel Leakage of Masked CMOS Gates
There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per cloc...
Stefan Mangard, Thomas Popp, Berndt M. Gammel
94
Voted
APCCAS
2002
IEEE
157views Hardware» more  APCCAS 2002»
15 years 3 months ago
Multiplier energy reduction through bypassing of partial products
Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital mul...
Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue
91
Voted
VTS
1997
IEEE
86views Hardware» more  VTS 1997»
15 years 2 months ago
Methods to reduce test application time for accumulator-based self-test
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...
Albrecht P. Stroele, Frank Mayer