The traditional approach to validate analog circuits is to utilize extensive SPICElevel simulations. The main challenge of this approach is knowing when all important corner cases...
Chris J. Myers, Reid R. Harrison, David Walter, Ni...
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
: Asynchronous circuits are often presented as a means of achieving low power operation. We investigate their suitability for low-energy applications, where long battery life and d...
Probabilistic CMOS is considered a promising technology for future generations of computing devices. By embracing possibly incorrect calculations, the technology makes it possible ...
Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Aru...