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DAC
2002
ACM
15 years 11 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
ISCAS
2002
IEEE
103views Hardware» more  ISCAS 2002»
15 years 2 months ago
A SPICE model for single electronics
With single-electron tunneling (SET) technology it is possible to build electronic circuits with extreme low power properties. These SET circuits must therefore operate in the sin...
R. van de Haar, J. Hoekstra, R. H. Klunder
DAC
2008
ACM
14 years 11 months ago
Technology exploration for graphene nanoribbon FETs
Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics because of their excellent carrier transport properties and potential for large scale proc...
Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik...
MTV
2007
IEEE
166views Hardware» more  MTV 2007»
15 years 4 months ago
Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits
Abstract—Abstract models of analog/mixed-signal (AMS) circuits can be used for formal verification and system-level simulation. The difficulty of creating these models preclude...
Scott Little, Alper Sen, Chris J. Myers
DAC
1995
ACM
15 years 1 months ago
The Validity of Retiming Sequential Circuits
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
Vigyan Singhal, Carl Pixley, Richard L. Rudell, Ro...