This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer d...
Abstract: We describe a technique to estimate the energy consumed by speed-independent asynchronous (clockless) control circuits. Because speed-independent circuits are hazard-free...
Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar
—This paper presents and compares three circuit architectures that are promising candidates to efficiently and dynamically supply GSM and EDGE RF power amplifiers in handsets. Th...
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...