Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee...
— In this study, two chaotic circuits coupled by a time-varying resistor are investigated. We assume that the timevarying resistor is realized by switching a positive and a negat...
The effect of shield structures for local wirings of analog integrated circuits on crosstalk is determined by electromagnetic simulation. The crosstalk of parallel wirings is redu...