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ICCAD
2000
IEEE
88views Hardware» more  ICCAD 2000»
15 years 2 months ago
Hierarchical Interconnect Circuit Models
The increasing size of integrated systems combined with deep submicron physical modeling details creates an explosion in RLC interconnect modeling complexity of unmanageable propo...
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pi...
GLVLSI
2005
IEEE
125views VLSI» more  GLVLSI 2005»
15 years 3 months ago
Low-power circuits using dynamic threshold devices
We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and perfor...
Paul Beckett
PATMOS
2004
Springer
15 years 3 months ago
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
Peter Celinski, Derek Abbott, Sorin Cotofana
EH
2003
IEEE
127views Hardware» more  EH 2003»
15 years 3 months ago
Comparing Different Serial and Parallel Heuristics to Design Combinational Logic Circuits
In this paper, we perform a comparative study of different heuristics used to design combinational logic circuits. The use of local search hybridized with a genetic algorithm and ...
Carlos A. Coello Coello, Enrique Alba, Gabriel Luq...
DATE
2002
IEEE
126views Hardware» more  DATE 2002»
15 years 2 months ago
Automated Modeling of Custom Digital Circuits for Test
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
Soumitra Bose