1304 search results - page 70 / 261 » Simulation of Soliton Circuits |
ITC
1996
IEEE
15 years 2 months ago
1996
IEEE
A novel approach to testing CMOS digital circuits is presented that is based on an analysis of IDD switching transients on the supply rails and voltage transients at selected test...
SBCCI
2006
ACM
15 years 3 months ago
2006
ACM
This paper presents a transistor optimization methodology for low-power analog integrated CMOS circuits, relying on the physics-based gm/ID characteristics as a design optimizatio...
110
click to vote
CHES
2005
Springer
15 years 3 months ago
2005
Springer
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate...
101
click to vote
ISCAS
2003
IEEE
15 years 3 months ago
2003
IEEE
We present an equation-based transistor size optimizer that minimizes delay of custom circuits. Our method uses static timing analysis to find the critical paths and numerical met...
ISVLSI
2003
IEEE
15 years 3 months ago
2003
IEEE
SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly incre...