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GLVLSI
2003
IEEE
194views VLSI» more  GLVLSI 2003»
15 years 3 months ago
RF CMOS circuit optimizing procedure and synthesis tool
In this paper, we discuss a methodology to design and synthesize analog CMOS components such as RF amplifiers. The inputs of the synthesis tool are the circuit specifications desc...
Chandrasekar Rajagopal, Karthik Sridhar, Adrian Nu...
ISMVL
2003
IEEE
111views Hardware» more  ISMVL 2003»
15 years 3 months ago
Modeling Multi-Valued Circuits in SystemC
The complexity of todays hardware systems steadily increases. Due to this fact new ways of efficiently describing systems are investigated. A very promising approach in this area...
Daniel Große, Görschwin Fey, Rolf Drech...
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
15 years 3 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
15 years 2 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
15 years 2 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag