1304 search results - page 76 / 261 » Simulation of Soliton Circuits |
ISCAS
2008
IEEE
15 years 4 months ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
DATE
2007
IEEE
15 years 4 months ago
2007
IEEE
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...
APCCAS
2006
IEEE
15 years 4 months ago
2006
IEEE
—A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bi...
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ICRA
2005
IEEE
15 years 3 months ago
2005
IEEE
- We previously proposed a new 3D form display actuated by shape memory alloy (SMA), which is capable of displaying large scale objects sequentially. Based on our devised method, o...
ISCAS
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, an analog implementation of the Wavelet Transform (WT) is presented. The circuit is based on the Dynamic Translinear (DTL) circuit technique and implements, by mean...