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» Simulation of Soliton Circuits
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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
15 years 3 months ago
Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
ISLPED
2004
ACM
107views Hardware» more  ISLPED 2004»
15 years 3 months ago
Characterizing and modeling minimum energy operation for subthreshold circuits
Subthreshold operation is emerging as an energy-saving approach to many new applications. This paper examines energy minimization for circuits operating in the subthreshold region...
Benton H. Calhoun, Anantha Chandrakasan
ISQED
2003
IEEE
73views Hardware» more  ISQED 2003»
15 years 3 months ago
A Novel Clocking Strategy for Dynamic Circuits
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim
VTS
2003
IEEE
87views Hardware» more  VTS 2003»
15 years 3 months ago
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits
We present a novel analog checker that adjusts dynamically the error threshold to the magnitude of its input signals. We demonstrate that this property is crucial for accurate con...
Haralampos-G. D. Stratigopoulos, Yiorgos Makris
DATE
1999
IEEE
73views Hardware» more  DATE 1999»
15 years 2 months ago
Design For Testability Method for CML Digital Circuits
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
Bernard Antaki, Yvon Savaria, Nanhan Xiong, Saman ...