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ISMVL
1994
IEEE
96views Hardware» more  ISMVL 1994»
15 years 2 months ago
Performance of CMOS Current Mode Full Adders
We present the performance of three different multivalued current mode 1-bit adders. These circuits have been simulated with the electrical parameters of a
Keivan Navi, A. Kazeminejad, Daniel Etiemble
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 4 months ago
A novel self-healing methodology for RF Amplifier circuits based on oscillation principles
— This paper proposes a novel self-healing methodology for embedded RF Amplifiers (LNAs) in RF sub-systems. The proposed methodology is based on oscillation principles in which t...
Abhilash Goyal, Madhavan Swaminathan, Abhijit Chat...
ISQED
2007
IEEE
197views Hardware» more  ISQED 2007»
15 years 4 months ago
A Simple Flip-Flop Circuit for Typical-Case Designs for DFM
The deep submicron (DSM) semiconductor technologies will make the worst-case design impossible, since they can not provide design margins that it requires. Research directions sho...
Toshinori Sato, Yuji Kunitake
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
15 years 3 months ago
Implicit and Exact Path Delay Fault Grading in Sequential Circuits
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, S...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi,...