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» Simulation of Soliton Circuits
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DAC
2005
ACM
15 years 11 months ago
Architecture-adaptive range limit windowing for simulated annealing FPGA placement
Previous research has shown both theoretically and practically that simulated annealing can greatly benefit from the incorporation of an adaptive range limiting window to control ...
Kenneth Eguro, Scott Hauck, Akshay Sharma
FDL
2003
IEEE
15 years 3 months ago
Using Symbolic Simulation for Bounded Property Checking
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
Jürgen Ruf, Prakash Mohan Peranandam, Thomas ...
BMAS
2000
IEEE
15 years 2 months ago
Modeling and Simulation of a Sigma-Delta Digital to Analog Converter Using VHDL-AMS
— Sigma-Delta digital to analog converters are less vulnerable to circuit imperfections than their A/D counterparts because they have their noise-shaping loop all in the digital ...
Martin Vogels, Bart De Smedt, Georges G. E. Gielen
ACSD
1998
IEEE
90views Hardware» more  ACSD 1998»
15 years 2 months ago
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [...
Miroslav N. Velev, Randal E. Bryant
ICISC
2008
103views Cryptology» more  ICISC 2008»
14 years 11 months ago
Generalized Universal Circuits for Secure Evaluation of Private Functions with Application to Data Classification
Secure Evaluation of Private Functions (PF-SFE) allows two parties to compute a private function which is known by one party only on private data of both. It is known that PF-SFE c...
Ahmad-Reza Sadeghi, Thomas Schneider 0003