One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the res...
Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
Models for the local anodic oxidation of silicon using scanning tunneling microscopy and non-contact atomic force microscopy are implemented in a generic process simulator, using ...
Lado Filipovic, Hajdin Ceric, Johann Cervenka, Sie...
Much contemporary development process research is based on analyses of process steps, their duration, and the events they propagate. Our initial research in large, mature telecomm...
The what-if analysis process is essential in symbiotic simulation systems. It is responsible for creating a number of alternative what-if scenarios and evaluating their performanc...
Heiko Aydt, Stephen John Turner, Wentong Cai, Malc...