719 search results - page 121 / 144 » Sizing router buffers |
121
Voted
JSA
2007
15 years 11 days ago
2007
Mapping of applications on a Multiprocessor System-on-Chip (MP-SoC) is a crucial step to optimize performance, energy and memory constraints at the same time. The problem is formu...
97
Voted
ALGORITHMICA
2002
15 years 10 days ago
2002
In recent years there has been an upsurge of interest in spatial databases. A major issue is how to manipulate efficiently massive amounts of spatial data stored on disk in multidi...
106
Voted
MICRO
2002
IEEE
15 years 4 days ago
2002
IEEE
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
88
Voted
TON
2002
15 years 3 days ago
2002
The min-plus theory of greedy shapers has been developed after Cruz's results on the calculus of network delays. An example of greedy shaper is the buffered leaky bucket cont...
97
Voted
INFOCOM
2005
IEEE
15 years 6 months ago
2005
IEEE
— The recent trend of rapid increase in routing table sizes at routers comprising the Internet’s core is posing a serious challenge to the current Internet’s scalability, ava...