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111
Voted
DATE
2003
IEEE
104views Hardware» more  DATE 2003»
15 years 5 months ago
Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...
George Lykakis, N. Mouratidis, Kyriakos Vlachos, N...
92
Voted
AINA
2009
IEEE
15 years 5 months ago
An Analytical Performance Evaluation for WSNs Using Loop-Free Bellman Ford Protocol
—Although several analytical models have been proposed for wireless sensor networks (WSNs) with different capabilities, very few of them consider the effect of general service di...
Mohammad Baharloo, Reza Hajisheykhi, Mohammad Arjo...
DATE
2002
IEEE
166views Hardware» more  DATE 2002»
15 years 5 months ago
Event Model Interfaces for Heterogeneous System Analysis
Complex embedded systems consist of hardware and software components from different domains, such as control and signal processing, many of them supplied by different IP vendors. ...
Kai Richter, Rolf Ernst
106
Voted
INFOCOM
2002
IEEE
15 years 5 months ago
Stochastic Analysis of Some Expedited Forwarding Networks
Abstract— We consider stochastic guarantees for networks with aggregate scheduling, in particular, Expedited Forwarding (EF). Our approach on the assumption that a node can be ab...
Milan Vojnovic, Jean-Yves Le Boudec
ISCA
2002
IEEE
80views Hardware» more  ISCA 2002»
15 years 5 months ago
A Large, Fast Instruction Window for Tolerating Cache Misses
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson K...