719 search results - page 128 / 144 » Sizing router buffers |
102
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SCCC
1997
IEEE
15 years 4 months ago
1997
IEEE
In a database system, read operations are much more common than write operations, and consequently, database systems have been read optimized. As the size of main memory increases...
ISCA
1993
IEEE
15 years 4 months ago
1993
IEEE
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a tran...
96
Voted
ASPDAC
2007
ACM
15 years 4 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
CODES
2004
IEEE
15 years 4 months ago
2004
IEEE
We present a analytical framework to identify the tradeoffs and performance impacts associated with different SoC platform configurations in the specific context of implementing m...
87
Voted
EUC
2006
Springer
15 years 4 months ago
2006
Springer
Mobile devices have difficulty in sustaining various services as in a wired environment, due to the storage shortage of the mobile device. The research[8] which provides remote sto...