719 search results - page 58 / 144 » Sizing router buffers |
121
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DAC
2010
ACM
14 years 10 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
138
Voted
INFOCOM
1998
IEEE
15 years 4 months ago
1998
IEEE
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
160
Voted
HPCA
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper compares the performance of hierarchical ring- and mesh-connected wormhole routed shared memory multiprocessor networks in a simulation study. Hierarchical rings are in...
88
Voted
ICCD
2003
IEEE
15 years 9 months ago
2003
IEEE
We consider several approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain the commited register values. The first ...
86
Voted
ICCS
2004
Springer
15 years 6 months ago
2004
Springer
Communication latencies have been identified as one of the performance limiting factors of message passing applications in clusters of workstations/multiprocessors. On the receiver...