719 search results - page 59 / 144 » Sizing router buffers |
102
Voted
DFT
2003
IEEE
15 years 5 months ago
2003
IEEE
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
108
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SIBGRAPI
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper describes a real-time shadow generation algorithm for polygonal environments illuminated by movable point light sources. The main goal is to quickly reduce the number o...
106
Voted
INFOCOM
2011
IEEE
14 years 4 months ago
2011
IEEE
—The main approaches to high speed measurement in routers are traffic sampling, and sketching. However, it is not known which paradigm is inherently better at extracting informa...
102
Voted
HPCA
2009
IEEE
15 years 7 months ago
2009
IEEE
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
98
Voted
NETWORKING
2010
15 years 2 months ago
2010
Rate-Delay (RD) Network Services constitute a promising differentiated-services architecture for multi-provider networks, by offering users a choice between high throughput or low ...