719 search results - page 8 / 144 » Sizing router buffers |
ASPDAC
2000
ACM
15 years 4 months ago
2000
ACM
- This paper presents software synthesis techniques to deal with non-primitive data type from graphical dataflow programs based on the synchronous dataflow (SDF) model. Non-primiti...
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both ...
109
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NOCS
2010
IEEE
14 years 10 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
95
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ANCS
2007
ACM
15 years 4 months ago
2007
ACM
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron VLSI designs. Recent research into the optimization of NoC architec...
130
Voted
TVLSI
2008
15 years 9 days ago
2008
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...