719 search results - page 97 / 144 » Sizing router buffers |
111
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MICRO
2006
IEEE
15 years 6 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
115
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VLSISP
2008
15 years 13 days ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
90
Voted
INFOCOM
2010
IEEE
14 years 11 months ago
2010
IEEE
Abstract— Robustness and reliability are critical issues in network management. To provide resiliency, a popular protection scheme against network failures is the simultaneous ro...
110
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VLSID
2007
IEEE
16 years 28 days ago
2007
IEEE
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
SIPEW
2009
Springer
15 years 7 months ago
2009
Springer
The M/G/1 queue is a classical model used to represent a large number of real-life computer and networking applications. In this note, we show that, for coefficients of variation o...