719 search results - page 98 / 144 » Sizing router buffers |
DATE
2008
IEEE
15 years 7 months ago
2008
IEEE
In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploratio...
120
Voted
ICNS
2007
IEEE
15 years 6 months ago
2007
IEEE
We study the performance of ant routing for static and dynamic network topologies. We also compare the performance of ant routing with AODV and DSR for ad hoc networks. The simula...
107
Voted
ASAP
2006
IEEE
15 years 6 months ago
2006
IEEE
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
116
Voted
GLVLSI
2006
IEEE
15 years 6 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
ISQED
2005
IEEE
15 years 6 months ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...