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ISPA
2007
Springer
15 years 3 months ago
Binomial Graph: A Scalable and Fault-Tolerant Logical Network Topology
The number of processors embedded in high performance computing platforms is growing daily to solve larger and more complex problems. The logical network topologies must also suppo...
Thara Angskun, George Bosilca, Jack Dongarra
DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 4 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
IEEEPACT
2007
IEEE
15 years 4 months ago
Error Detection Using Dynamic Dataflow Verification
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
Albert Meixner, Daniel J. Sorin
DAC
2006
ACM
14 years 11 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
IEEEPACT
2007
IEEE
15 years 4 months ago
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking
Under current worst-case design practices, manufacturers specify conservative values for processor frequencies in order to guarantee correctness. To recover some of the lost perfo...
Brian Greskamp, Josep Torrellas