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GLVLSI
2010
IEEE
156views VLSI» more  GLVLSI 2010»
15 years 2 months ago
A multi-level approach to reduce the impact of NBTI on processor functional units
NBTI is one of the most important silicon reliability problems facing processor designers today. The impact of NBTI can be mitigated at both the circuit and microarchitecture leve...
Taniya Siddiqua, Sudhanva Gurumurthi
ASPLOS
2009
ACM
15 years 10 months ago
Mixed-mode multicore reliability
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
Philip M. Wells, Koushik Chakraborty, Gurindar S. ...
HIPC
2004
Springer
15 years 3 months ago
Lock-Free Parallel Algorithms: An Experimental Study
Abstract. Lock-free shared data structures in the setting of distributed computing have received a fair amount of attention. Major motivations of lock-free data structures include ...
Guojing Cong, David A. Bader
ASPLOS
2009
ACM
15 years 10 months ago
Understanding software approaches for GPGPU reliability
Even though graphics processors (GPUs) are becoming increasingly popular for general purpose computing, current (and likely near future) generations of GPUs do not provide hardwar...
Martin Dimitrov, Mike Mantor, Huiyang Zhou
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
15 years 4 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...