11 search results - page 2 / 3 » Soft Error Rate Analysis for Combinational Logic Using An Ac... |
ICCAD
2007
IEEE
14 years 3 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
VLSID
2006
IEEE
14 years 6 months ago
2006
IEEE
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
ICCAD
2004
IEEE
14 years 3 months ago
2004
IEEE
— A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates...
ISQED
2006
IEEE
14 years 10 days ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
VTS
2007
IEEE
14 years 17 days ago
2007
IEEE
Soft errors due to cosmic particles are a growing reliability threat for VLSI systems. In this paper we analyze the soft error vulnerability of FPGAs used in storage systems. Sinc...