49 search results - page 3 / 10 » Soft error derating computation in sequential circuits |
110
Voted
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
100
Voted
DSN
2002
IEEE
15 years 4 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
ISQED
2006
IEEE
15 years 5 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
DSN
2008
IEEE
15 years 6 months ago
2008
IEEE
As semiconductor technology scales, reliability is becoming an increasingly crucial challenge in microprocessor design. The rSRAM and voltage scaling are two promising circuit-lev...