49 search results - page 5 / 10 » Soft error derating computation in sequential circuits |
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
VLSID
2008
IEEE
15 years 12 months ago
2008
IEEE
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
DATE
2005
IEEE
15 years 5 months ago
2005
IEEE
In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits based on error propagation probability (EPP) computation. Exper...
ISQED
2009
IEEE
15 years 6 months ago
2009
IEEE
With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of th...
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DAC
2005
ACM
15 years 1 months ago
2005
ACM
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...