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» Soft error derating computation in sequential circuits
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VLSID
2006
IEEE
156views VLSI» more  VLSID 2006»
15 years 12 months ago
SEAT-LA: A Soft Error Analysis Tool for Combinational Logic
Radiation induced soft errors in combinational logic is expected to become as important as directly induced errors on state elements. Consequently, it has become important to deve...
Jungsub Kim, Mary Jane Irwin, Narayanan Vijaykrish...
VLSID
2009
IEEE
87views VLSI» more  VLSID 2009»
16 years 6 days ago
Soft Error Rates with Inertial and Logical Masking
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
Fan Wang, Vishwani D. Agrawal
DAC
2009
ACM
16 years 18 days ago
Improving testability and soft-error resilience through retiming
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
VLSID
2005
IEEE
255views VLSI» more  VLSID 2005»
15 years 12 months ago
Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks
We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher ord...
Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. ...
DAC
1998
ACM
15 years 3 months ago
Efficient Analog Test Methodology Based on Adaptive Algorithms
This papers describes a new, fast and economical methodology to test linear analog circuits based on adaptive algorithms. To the authors knowledge, this is the first time such tec...
Luigi Carro, Marcelo Negreiros