49 search results - page 9 / 10 » Soft error derating computation in sequential circuits |
GLOBECOM
2008
IEEE
15 years 6 months ago
2008
IEEE
Abstract—Consider a communications system where the detector generates a mix of hard and soft outputs, which are then fed into a soft-input channel decoder. In such a setting, it...
GLVLSI
2009
IEEE
15 years 3 months ago
2009
IEEE
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
DFT
2007
IEEE
15 years 6 months ago
2007
IEEE
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...