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» Soft-output sphere decoding: algorithms and VLSI implementat...
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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 2 months ago
High-speed VLSI architecture for parallel Reed-Solomon decoder
—This paper presents high-speed parallel Reed–Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber op...
Hanho Lee
68
Voted
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 1 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
ISVLSI
2005
IEEE
115views VLSI» more  ISVLSI 2005»
15 years 3 months ago
High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization
The authors present a turbo soft-in soft-out (SISO) decoder based on Max-Log maximum a posteriori (ML-MAP) algorithm implemented with sliding window (SW) method. A novel technique...
J. H. Han, Ahmet T. Erdogan, Tughrul Arslan
SIPS
2007
IEEE
15 years 3 months ago
MIMO Detector Based on Viterbi Algorithm
: - Suboptimal detectors of multiple-input multiple-output (MIMO) have been studied because the implementation of the optimum detector, the maximum-likelihood (ML) detector, has so...
Jin Lee, Sin-Chong Park
FCCM
2004
IEEE
91views VLSI» more  FCCM 2004»
15 years 1 months ago
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision ReedSolomon decoding algorithm. The key feature is the embedding of b...
Warren J. Gross, Frank R. Kschischang, P. Glenn Gu...