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210
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TII
2011
206views Education» more  TII 2011»
14 years 10 months ago
Timing-Failure Risk Assessment of UML Design Using Time Petri Net Bound Techniques
Abstract—Software systems that do not meet their timing constraints can cause risks. In this work, we propose a comprehensive method for assessing the risk of timing failure by e...
Simona Bernardi, Javier Campos, José Merseg...
127
Voted
ACTAC
2002
99views more  ACTAC 2002»
15 years 3 months ago
Recognizing Design Patterns in C++ Programs with the Integration of Columbus and Maisa
A method for recognizing design patterns from C++ programs is presented. The method consists of two separate phases, analysis and reverse engineering of the C++ code, and architec...
Rudolf Ferenc, Juha Gustafsson, Lászl&oacut...
PFE
2001
Springer
15 years 8 months ago
Introducing Product Lines in Small Embedded Systems
: How do you introduce product lines into a hardware dominated organization that has increasing software architecture awareness and products with extremely limited memory resources...
Christoph Stoermer, Markus Roeddiger
239
Voted
EUROSYS
2011
ACM
14 years 7 months ago
Database engines on multicores, why parallelize when you can distribute?
Multicore computers pose a substantial challenge to infrastructure software such as operating systems or databases. Such software typically evolves slower than the underlying hard...
Tudor-Ioan Salomie, Ionut Emanuel Subasu, Jana Gic...
139
Voted
SBCCI
2003
ACM
213views VLSI» more  SBCCI 2003»
15 years 9 months ago
Algorithms and Tools for Network on Chip Based System Design
Network on Chip (NoC) is a new paradigm for designing core based System on Chips. It supports high degree of reusability and is scalable. In this paper, an efficient Two-Step Gene...
Tang Lei, Shashi Kumar