Sciweavers

2153 search results - page 230 / 431
» Software Architectures for Task-Oriented Computing
Sort
View
BIRTHDAY
2003
Springer
15 years 9 months ago
Comet in Context
Combinatorial optimization problems naturally arise in many application areas, including logistics, manufacturing, supplychain management, and resource allocation. They often give...
Laurent Michel, Pascal Van Hentenryck
DAC
2002
ACM
16 years 5 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
ICNP
2009
IEEE
15 years 10 months ago
Better by a HAIR: Hardware-Amenable Internet Routing
—Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significan...
Firat Kiyak, Brent Mochizuki, Eric Keller, Matthew...
136
Voted
POPL
2010
ACM
15 years 2 months ago
S-Net for multi-memory multicores
S-NET is a declarative coordination language and component technology aimed at modern multi-core/many-core architectures and systems-on-chip. It builds on the concept of stream pr...
Clemens Grelck, Jukka Julku, Frank Penczek
VLSID
2007
IEEE
231views VLSI» more  VLSID 2007»
16 years 4 months ago
AHIR: A Hardware Intermediate Representation for Hardware Generation from High-level Programs
We present AHIR, an intermediate representation (IR), that acts as a transition layer between software compilation and hardware synthesis. Such a transition layer is intended to t...
Sameer D. Sahasrabuddhe, Hakim Raja, Kavi Arya, Ma...