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» Software Cache Coherence for Large Scale Multiprocessors
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ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
15 years 3 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...
IPPS
2000
IEEE
15 years 1 months ago
Fault-Tolerant Distributed-Shared-Memory on a Broadcast-Based Interconnection Network
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
Diana Hecht, Constantine Katsinis
CAL
2007
14 years 9 months ago
A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed memory hierarchy enhancements for coher...
Jason Zebchuk, Andreas Moshovos
IPPS
2010
IEEE
14 years 6 months ago
Clustering JVMs with software transactional memory support
Affordable transparent clustering solutions to scale non-HPC applications on commodity clusters (such as Terracotta) are emerging for Java Virtual Machines (JVMs). Working in this ...
Christos Kotselidis, Mikel Luján, Mohammad ...
HPCA
2001
IEEE
15 years 9 months ago
JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers
We propose methods for reducing the energy consumed by snoop requests in snoopy bus-based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops do not ...
Andreas Moshovos, Gokhan Memik, Babak Falsafi, Alo...