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INTEGRATION
2008
127views more  INTEGRATION 2008»
15 years 3 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
ICDCSW
2003
IEEE
15 years 9 months ago
Service Discovery and Name Resolution Architectures for On-Demand MANETs
Discovery of services and other named resources is expected to be a crucial feature for the usability of mobile ad-hoc networks (MANETs). In this paper, we propose a mechanism for...
Paal Engelstad, Yan Zheng, Tore E. Jønvik, ...
APCCAS
2006
IEEE
224views Hardware» more  APCCAS 2006»
15 years 10 months ago
A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding
We propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. We use two intra prediction units to increase the performance...
Yu-Chien Kao, Huang-Chih Kuo, Yin-Tzu Lin, Chia-We...
ICECCS
1997
IEEE
114views Hardware» more  ICECCS 1997»
15 years 8 months ago
An approach to integration testing based on architectural descriptions
Software architectures can play a role in improving the testing process of complex systems. In particular, descriptions of the software architecture can be useful to drive integra...
Antonia Bertolino, Paola Inverardi, Henry Muccini,...
IWPC
2009
IEEE
15 years 11 months ago
The loss of architectural knowledge during system evolution: An industrial case study
Architecture defines the components of a system and their dependencies. The knowledge about how the architecture is intended to be implemented is essential to keep the system str...
Martin Feilkas, Daniel Ratiu, Elmar Jürgens