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LCTRTS
2007
Springer
15 years 11 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
CODES
2006
IEEE
15 years 11 months ago
Fuzzy decision making in embedded system design
The use of Application Specific Instruction-set Processors (ASIP) is a solution to the problem of increasing complexity in embedded systems design. One of the major challenges in...
Alessandro G. Di Nuovo, Maurizio Palesi, Davide Pa...
139
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CODES
2005
IEEE
15 years 10 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
UIST
2004
ACM
15 years 10 months ago
Hierarchical parsing and recognition of hand-sketched diagrams
A long standing challenge in pen-based computer interaction is the ability to make sense of informal sketches. A main difficulty lies in reliably extracting and recognizing the i...
Levent Burak Kara, Thomas F. Stahovich
PLDI
2003
ACM
15 years 10 months ago
Automatically proving the correctness of compiler optimizations
We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. We first present a domainspeci...
Sorin Lerner, Todd D. Millstein, Craig Chambers
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