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LCTRTS
2009
Springer
15 years 10 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...
132
Voted
LCTRTS
2009
Springer
15 years 10 months ago
Live-range unsplitting for faster optimal coalescing
Register allocation is often a two-phase approach: spilling of registers to memory, followed by coalescing of registers. Extreme liverange splitting (i.e. live-range splitting aft...
Sandrine Blazy, Benoît Robillard
CODES
2009
IEEE
15 years 10 months ago
FRA: a flash-aware redundancy array of flash storage devices
Since flash memory has many attractive characteristics such as high performance, non-volatility, low power consumption and shock resistance, it has been widely used as storage med...
Yangsup Lee, Sanghyuk Jung, Yong Ho Song
148
Voted
CODES
2009
IEEE
15 years 10 months ago
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
Time redundancy (rollback-recovery) and hardware redundancy are commonly used in real-time systems to achieve fault tolerance. From an energy consumption point of view, time redun...
Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles
118
Voted
ISCA
2009
IEEE
137views Hardware» more  ISCA 2009»
15 years 10 months ago
A case for an interleaving constrained shared-memory multi-processor
Shared-memory multi-threaded programming is inherently more difficult than single-threaded programming. The main source of complexity is that, the threads of an application can in...
Jie Yu, Satish Narayanasamy
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